Enable Logic Analizer and it should be waiting for the trigger signals. Set the DIO1 trigger to low and from trigger settings set Trigger Logic to AND.ĭIO2 does not need a trigger setting as it is the output signal of the ADC. As the CS# falling edge initiates the data transfer, you should set the trigger of DIO0 to falling edge. Set the group channel as SPI and the cannels to corresponding SPI signals.ĭIO0 as CS#, DIO1 as CLK and DIO2 as MISO. In Logic Analyzer configure DIO0, DIO1 and DIO2 as a group channel. ![]() Vin (channel 1) and Vref(channel 2) voltages The point where the code changes from ones to zeros is the point at which the input signal becomes smaller than the respective comparator reference-voltage levels.Ĭonsider the circuit presented in Figure 6.įigure 23. Each comparator produces a 1 when its analog input voltage is higher than the reference voltage applied to it. A resistive-divider with 2N resistors provides the reference voltage. ![]() For an N-bit converter, the circuit employs 2N-1 comparators. Typical examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives.įlash ADCs are made by cascading high-speed comparators. Flash ADCs are ideal for applications requiring very large bandwidth, but they consume more power than other ADC architectures and are generally limited to 8-bit resolution. Flash analog-to-digital converters, also known as parallel ADCs, are one of the fastest way to convert an analog signal to a digital signal.
0 Comments
Leave a Reply. |